Query aboutSVpackages

[nskp007]

Hi

I have a design that has mixture of SV and Verilog Files . can I include verilog files inside a package i.e


package my_pkg

{
`include my_file_1.sv
`include my_file_2.sv
.
.
.
`include my_file_10.v
}

and then import the pkg as


import my_pkg :: *


Is it permissible. I mean does it have any compile time or run time problems


Rgds
Nskp

[dave_59]

Please see 1365, or search this forum for the words import include package.

[nskp007]

Thanks Dave

But I would request you to please make thing clearer in a rather simple language as i am too young to SV.

What i get is that i cannot include verilog files with SV files due to compile time errors as packages are compiled separately and this will clash with module definitions having always and initial block.

Rgds
nskp

[dave_59]

Nskp,

This forum is no substitute for proper Verilog or SystemVerilog training. I will tell you that `include does not care what kind of file it includes; it's just a text file. All that matters is that after the text is included, you have proper SystemVerilog syntax. You could `include every line of a module from separate files if you wanted to.

My point is that packages do not allow modules and do not need to. Whether they are separately compile is irrelevant. You may also want to read this http://blogs.mentor.com/nosimulation/blog/2009/09/25/unit-vs-root/

Dave

[nskp007]

Thanks Dave such a Help