How is it Open?

The OVM is available as a download by anyone, under the Apache 2.0 license. This standard, open license allows anyone to use OVM libraries for any purpose, including creation of derivative work.

Who created OVM?

The OVM is the result of joint development between Cadence and Mentor Graphics to facilitate true SystemVerilog interoperability with a standard library and a proven methodology. Completely open, it combines the best of the Cadence® Incisive® Plan-to-Closure Universal Reuse Methodology (URM) and the Mentor Advanced Verification Methodology (AVM), and is usable on two-thirds of the world's SystemVerilog simulators. The OVM will also facilitate the development and usage of plug-and-play verification IP (VIP) written in SystemVerilog (IEEE 1800), SystemC® (IEEE 1666), and e (IEEE 1647) languages.

When is it available?

The OVM is available for download from this site as of January 9. 2008. Join OVM World today to get regular updates on the OVM.

Background

Despite the availability of the IEEE 1800 SystemVerilog standard, the benefits of an open verification language have not yet been realized. The availability of multiple class libraries and methodologies have hurt the ability for true interoperability.

• Multiple class-libraries restricted interoperability
• Different language subsets
• Incompatible VIP interfaces
• Linked to just one simulator

• Multiple methodologies restricted reuse
• Prohibitive licensing limited multi-vendor support
• Incomplete and incompatible technology restricted VIP plug & play (e.g. communication, messaging and synchronization, test-writer I/F, etc.)
• Different availability of underlying SystemVerilog language constructs prevented interoperability
• Different set of language constructs implemented in each simulator
• Different evaluation of those language constructs that were aligned

Cadence and Mentor Graphics have collaborated to address these issues and to deliver an open and interoperable class library and methodology, the OVM, which delivers on the SystemVerilog promise.

Key Benefits

• Open
• Written in IEEE 1800 SystemVerilog
• Runs on any simulator supporting the IEEE 1800 standard
• Verified on Cadence’s Incisive and Mentor Graphics’ Questa Verification Platform
• True open-source license agreement (Apache 2.0)

• Interoperable
• Ensures VIP interoperability across ecosystem & simulators
• Enables VIP ‘plug and play’ functionality for designers
• Ensures interoperability with other high level languages

• Proven
• Based on Cadence’s Incisive Plan-to-Closure Methodology - URM Component and Mentor’s Advanced Verification Methodology (AVM)
• Incorporates Best Practices from >10 years of experiences